Assignment1 with VHDL using Xilinx software version 10.1 Essay

Assignment1 with VHDL using Xilinx software version 10.1 - Essay Example A serial register operates serially, accepting and transferring data one bit at a time, while a parallel register operates on a parallel fashion accepting and transferring all the bits simultaneously. Since mere transferring or storing data in digital circuits is literally achieved by shifting the bits, the registers specifically used for storing and retrieval purposes without any manipulations, are called shift registers. A shift register is generally designed with a series of flip-flops connected in the form of a chain such that the output of one is connected to the input of the other expect the output of the last one which is the actual output of the circuit. A universal shift register is one that incorporates all the features that are applicable for shifting operations including parallel input/output, left/right-shift serial inputs, operating mode control inputs (S1 & S0) and direct overriding clear line (RESET), etc. 2. Design Overview For this assignment, a 4-bit universal shift register is designed in VHDL (VHSI Hardware Description Language) and simulated in VHDL IDE- Xilinx ISE. VHDL is generally used to write down the entire digital circuit description and its logic in the form of code or program. The circuit description is defined as entity and the logic as process. ... Schematic view of 4-bit universal Shift Register created in Xilinx ISE The input S1 and S0 act as control signals which determines the mode of operation of the shift register. The possible combination of the two signals along with the required mode of operation are summarised in the below table: S1 S0 Action 0 0 Hold (retain the previous state) 0 1 Shift left 1 0 Shift right 1 1 Parallel load 3. Design Solution Based on the above truth table for possible combinations of control signals, the state function table is derived for all combinations of input signals and control signals with respect to RESET and CLOCK signals and is summarised below: RESET Mode Clock Serial IN Parallel IN OUTPUTS _RST S1 S0 CLK SIL SIR D0 D1 D2 D3 Q3 Q2 Q1 Q0 0 X X X X X X X X X X X X X 1 X X Not ? X X X X X X Q3 Q2 Q1 Q0 0 0 0 ? X X X X X X Q3 Q2 Q1 Q0 0 0 1 ? 1 X X X X X Q2 Q1 Q0 1 0 0 1 ? 0 X X X X X Q2 Q1 Q0 0 0 1 0 ? X 1 X X X X 1 Q3 Q2 Q1 0 1 0 ? X 0 X X X X 0 Q3 Q2 Q1 0 1 1 ? X X D0 D1 D2 D3 Q0 Q1 Q2 Q3 X – don’t care condition low to high clock transition In order to achieve the above functionality using VHDL programming, behavioural approach of VHDL is employed in the process definition. This approach is chosen due to the fact that it is purely behaviour oriented and highly independent of the design implementations and will not change with changes in design approach for the same behaviour. The process is defined with the circuit’s behavioural architecture and the event attribute on the CLK signal is employed, to realize the clock signal state change. Since RESET signal is asynchronous and needs immediate action irrespective of the states of other inputs, RST is checked at the beginning of the process